Generally, for system-on-chip (SOC) applications, it is becoming very important to have a cost-effective process which provides for integration of low voltage complementary MOS (CMOS) for logic and intermediate (or medium) voltage devices for analog devices and for I/O interface stages. The I/O stages typically require high-speed switches and high-package density, which further require low on-resistance (e.g., low Rdson), high breakdown voltage (e.g., higher BVdss), and low Miller capacitance.
In addition, as higher-voltage devices integrate with core devices (which are lower-voltage devices) on the nanoscale, physical limits are being approached. For example, highly-doped source/drain implants, needed for the higher potentials on the higher-voltage devices, are being moved closer to the conducting channel, resulting in high leakage and substrate currents. Longer channel lengths must, therefore, be employed, which in turn degrade device performance. Similarly, the reduction in the thickness of poly-silicon layers and source/drain junctions to improve core device performance reduces electrostatic discharge (ESD) protection and leads to poly-silicon penetration during high energy LDD implants. However, limiting LDD implant energy conflicts with the high-voltage device requirement of deeper source/drain junctions to sustain higher I/O voltages.
FIG. 1 illustrates a common self-aligned metal oxide semiconductor (MOS) structure having a substrate 101 with shallow trench isolation (STI) regions 103a and 103b, lightly-doped (LDD) source/drain regions 105 and 106, more strongly-doped source/drain regions 107 and 108, and well region 109. A gate stack 111, positioned on the substrate 101, includes gate oxide layer 113, poly-silicon layer 115, and metal silicide layer 117. Spacers 119 and 121 separate the gate stack 111 from silicide 123 and 125 positioned over source/drain regions 107 and 108, respectively. The LDD regions 105 and 106 extend slightly underneath the gate oxide layer 113 at opposite sides of conductive channel 127 beneath gate 111. Although the structure is able to operate at intermediate voltages (e.g., voltages between 2.5 V and 5 V), a long channel length (e.g., 0.4 μm to 0.9 μm) is typically required to pass hot carrier injection, and the structure is unable to achieve sufficiently low on resistance even when the breakdown voltage is low. Moreover, since the width of spacers 119 and 121 is typically minimized to increase device density, highly-doped portions of the source and drain 105 and 107 are moved closer to the channel, resulting in higher substrate currents, which in turn may cause deleterious hot-carrier effects.
FIG. 2 illustrates an extended drain metal oxide semiconductor (EDMOS), another approach that has been proposed to overcome the difficulties with moving the highly-doped source/drain closer to the channel as package density is increased (i.e., the limitations of the structure in FIG. 1). Similar to FIG. 1, the structure in FIG. 2 includes a substrate 201 having a well region 203, LDD region 205 and highly-doped source region 207, a gate stack 209 including gate oxide 211, poly-silicon layer 213, and silicide 215, spacers 217a and 217b, silicide 219a and 219b, and STI regions 221a and 221b. The structure of FIG. 2 differs from that of FIG. 1 in that the LDD region 225 associated with drain region 229 is extended in the lateral direction both toward channel 227 and toward drain region 229, and highly doped drain region 229 is moved laterally away from channel 227. To accommodate the extended LDD region 225, a silicide block 231 is positioned between spacer 217b and silicide 219b. While this structure moves the highly-doped drain region 229 away from the channel 227, it suffers from certain disadvantages associated with the additional length added to the drain region. For example, since Rdson increases with device pitch (the length between successive gates on a device), and the additional length of the drain region effectively increases the pitch, Rdson tends to be high, making the structure less applicable for symmetrical use. Additionally, fabrication difficulties increase because the highly-doped drain region 229 is no longer self-aligned and the implant energy used to dope the LDD region 225 is limited by the thickness of the gate poly-silicon layer 213.
A need therefore exists for methodology enabling use of short channel lengths and high LDD implantation energy, not limited by poly-silicon thickness, and the resulting structure.